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| LTC1736 5-Bit Adjustable High Efficiency Synchronous Step-Down Switching Regulator FEATURES s s s s DESCRIPTIO December 1998 s s s s s s s s s s s Dual N-Channel MOSFET Synchronous Drive Synchronizable/Programmable Fixed Frequency Wide VIN Range: 3.5V to 36V Operation 5-Bit Digital-to-Analog VOUT Selection: 0.925V to 2.00V Range with 50mV/25mV Steps Very Low Dropout Operation: 99% Duty Cycle 1% 0.8V Reference Internal Current Foldback Output Overvoltage Crowbar Protection Latched Short-Circuit Shutdown Timer with Defeat Option Forced Continuous Control Pin Optional Programmable Soft-Start Remote Output Voltage Sense Logic Controlled Micropower Shutdown: IQ < 20A Power Good Output Voltage Monitor Available in 24-Lead SSOP Package The LTC(R)1736 is a synchronous step-down switching regulator controller optimized for CPU power. The output voltage is programmed by a 5-bit digital-to-analog converter (DAC) that adjusts the output voltage from 0.925V to 2.00V according to Intel mobile VID specifications. The 0.8V 1% reference is compatible with future microprocessor generations. The operating frequency (synchronizable up to 500kHz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. The output voltage is monitored by a power good window comparator that indicates when the output is within 7.5% of its programmed value. Protection features include: internal foldback current limiting, output overvoltage crowbar and optional short-circuit shutdown. Soft-start is provided by an external capacitor that can be used to properly sequence supplies. The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum). Pin defeatable Burst ModeTM operation provides high efficiency at low load currents while 99% duty cycle provides low dropout operation. APPLICATIO S s s s Notebook and Palmtop Computers, PDAs Power Supply for Mobile Pentium(R) II Processor Low Voltage Power Supplies , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. TYPICAL APPLICATIO COSC 43pF CSS 0.1F CC 330pF COSC VIN 7V TO 22V VIN TG RUN/SS SW ITH PGOOD B4 B3 B2 B1 B0 SGND LTC1736 INTVCC BOOST BG PGND DB CMDSH-3 CB 0.22F M1 Si4420DY + CIN 10F/50V x3 CERAMIC L1 1.5H RSENSE 0.004 RC 10k + 4.7F M2 Si4420DY x2 D1 MBRD835L VOSENSE SENSE - SENSE + 1000pF 100pF 1736 F01 Figure 1. High Efficiency Step-Down Converter Specifications on this data sheet are preliminary only, and subject to change without notice. Contact the manufacturer before finalizing a design using this part. U + U U VOUT 1.5V TO 1.75V 12A COUT 180F/4V x3 1 LTC1736 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW COSC RUN/SS ITH FCB SGND PGOOD SENSE - SENSE + VFB 1 2 3 4 5 6 7 8 9 24 TG 23 BOOST 22 SW 21 VIN 20 INTVCC 19 BG 18 PGND 17 EXTVCC 16 VIDVCC 15 B4 14 B3 13 B2 Input Supply Voltage (VIN).........................36V to - 0.3V Topside Driver Supply Voltage (BOOST)....42V to - 0.3V Switch Voltage (SW).....................................36V to - 5V EXTVCC, VIDVCC, (BOOST - SW) Voltages ..7V to - 0.3V SENSE +, SENSE - .......................... 1.5(INTVCC) to - 0.3V FCB Voltage ............................(INTVCC + 0.3V) to - 0.3V ITH, VOSENSE, VFB Voltage .........................2.7V to - 0.3V RUN/SS, B0 to B4, PGOOD Voltages ...........7V to - 0.3V Peak Driver Output Current <10s (TG, BG) .............. 3A INTVCC Output Current ......................................... 50mA Operating Ambient Temperature Range LTC1736C................................................ 0C to 70C LTC1736I ............................................ - 40C to 85C Junction Temperature (Note 2) ............................. 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER LTC1736CG LTC1736IG VOSENSE 10 B0 11 B1 12 G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 125C, JA = 110C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL IIN VFB VOSENSE VLINEREG VLOADREG PARAMETER Feedback Current Output Voltage Set Accuracy Reference Voltage Line Regulation Output Voltage Load Regulation Main Control Loop TA = 25C, VIN = 15V, VRUN/SS = 5V unless otherwise noted. MIN TYP 10 q CONDITIONS (Note 3) (Note 3) See Table 1 VIN = 3.6V to 30V (Note 3) (Note 3) Measured in Servo Loop; VITH = 0.5V Measured in Servo Loop; VITH = 2V VFCB = 0.8V (Note 4), EXTVCC = 5V 3.6V < VIN < 30V VRUN/SS = 0V, 3.6V < VIN < 15V VRUN/SS, Ramping Positive VRUN/SS, Ramping Negative VRUN/SS = 0V Soft Short Condition, VFB = 0.5V, VRUN/SS = 2V VFB = 0.5V, VRUN/SS = 3V Measured at VIN Pin VFB = 0.6V VSENSE- = VSENSE+ = 0.8V Tested with a Square Wave, VITH = 1.75V q q q MAX UNITS nA % %/V % % V A V A A V V A A A V mV A ns 1 0.002 0.2 - 0.2 0.8 - 0.25 0.86 450 15 1.3 3.5 2 -3 3 3.5 75 68 200 VFCB IFCB VOVL IQ Forced Continuous Threshold Forced Continuous Current Feedback Overvoltage Lockout Input DC Supply Current Normal Mode Shutdown Run Pin Start Threshold Run Pin Begin Latchoff Threshold Soft-Start Charge Current RUN/SS Discharge Current Shutdown Latch Disable Current Undervoltage Lockout Maximum Current Sense Threshold Sense Pins Total Source Current Minimum On-Time VRUN/SS VRUN/SS IRUN/SS ISCL ISDLHO UVLO VSENSE(MAX) ISENSE tON(MIN) 2 U W U U WW W LTC1736 ELECTRICAL CHARACTERISTICS SYMBOL TG tr TG tf BG tr BG tf VINTVCC VLDO(INT) VLDO(EXT) VEXTVCC Oscillator fOSC fH/fOSC fFCB(SYNC) PGOOD Output VPGL IPGOOD VPG PGOOD Voltage Low PGOOD Leakage Current PGOOD Trip Level Oscillator Frequency Maximum Sync Frequency Ratio FCB Pin Threshold For Sync PARAMETER TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time Internal VCC Voltage Internal VCC Load Regulation EXTVCC Drop Voltage EXTVCC Switchover Voltage TA = 25C, VIN = 15V, VRUN/SS = 5V unless otherwise noted. MIN TYP 50 50 50 50 5.2 0.15 150 4.7 300 1.3 1.2 0.4 1 - 7.5 7.5 2.7 5.5 70 7 10 40 0.4 1.0 0.01 2.8 4.5 Note 5: Oscillator frequency is tested by measuring the COSC charge current (IOSC) and applying the formula: -1 8.477(1011) 1 1 fOSC = + COSC (pF ) + 11 ICHG IDIS CONDITIONS CLOAD = 3000pF CLOAD = 3000pF CLOAD = 3000pF CLOAD = 3000pF ICC = 20mA, 6V < VIN < 30V, VEXTVCC = 4V ICC = 0mA to 20mA, VEXTVCC = 4V ICC = 20mA, VEXTVCC = 5V ICC = 20mA, EXTVCC Ramping Positive (Note 5), COSC = 43pF Ramping Positive IPGOOD = 1mA VPGOOD = 5V VOSENSE Respect to Set Output Voltage VOSENSE Ramping Positive VOSENSE Ramping Negative MAX UNITS ns ns ns ns V % mV V kHz V V A % % V A k % k V A V V Internal VCC Regulator VID Control VIDVCC IVIDVCC RVFB/VOSENSE RRATIO RPULL-UP VIDT IVIDLEAK VPULL-UP VID Operating Supply Voltage VID Supply Current Resistance Between VOSENSE and VFB Resistor Ratio Accuracy B0 to B4 Pull-Up Resistance VID Input Voltage Threshold VID Input Leakage Current VID Pull-Up Voltage (Note 7) VIDVCC < VID < 7V VIDVCC = 3.3V VIDVCC = 5V Programmed from 0.925V to 2.00V (Note 7) VDIODE = 0.6V (Note 6) VIDVCC = 3.3V - 0.25 150 13 0.25 1.6 1 The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1736CGN, LTC1736IGN: TJ = TA + (PD * 110C/W) Note 3: The LTC1736 is tested in a feedback loop that servos VOSENSE to the balance point for the error amplifier (VITH = 0.8V). Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: With all five inputs floating, the VIDVCC current is typically 100A. However, the VIDVCC current will rise and be approximately equal to the number of grounded VID input pins times (VIDVCC - 0.6V)/40k + 100A. (See the Applications Information section for more detail.) Note 7: Each built-in pull-up resistor attached to the VID inputs also has a series diode to allow input voltages higher than the VIDVCC supply without damage or clamping. (See the Applications Information section for more detail.) 3 LTC1736 PI FU CTIO S COSC (Pin 1): External capacitor COSC from this pin to ground sets the operating frequency. RUN/SS (Pin 2): Combination of Soft-Start and Run Control Inputs. A capacitor to ground at this pin sets the ramp time to full output current. The time is approximately 0.5s/F. Forcing this pin below 1.3V causes the device to be shut down. In shutdown all functions are disabled. Latchoff over current protection is also invoked via this pin as described in the Applications Information section. ITH (Pin 3): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 2.4V. FCB (Pin 4): Forced Continuous/Synchronization Input. Tie this pin to ground for continuous synchronous operation, to a resistive divider from the secondary output when using a secondary winding, or to INTVCC to enable Burst Mode operation at low load currents. Clocking this pin with a signal above 1.5VP-P disables Burst Mode operation but allows cycle skipping at low load currents and synchronizes the internal oscillator with the external clock. SGND (Pin 5): Small-Signal Ground. This pin must be routed separately from other grounds to the (-) terminal of COUT. PGOOD (Pin 6): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the VOSENSE pin is not within 7.5% of its set point. SENSE - (Pin 7): Connects to the (-) Input of the Current Comparator. SENSE + (Pin 8): The (+) Input to the Current Comparator. Built-in offsets between SENSE - and SENSE + pins in conjunction with RSENSE set the current trip threshold. VFB (Pin 9): Divided Down VOSENSE Voltage Feeding the Error Amplifier of the Regulator. The VID inputs program a resistive divider between VOSENSE and SGND; the tap point on the divider is VFB . The voltage on VFB is 0.8V when the output is in regulation. Normally this pin is bypassed to SGND with 100pF. VOSENSE (Pin 10): Receives the remotely sensed feedback voltage from the output. B0 to B4 (Pins 11 to 15): Digital Inputs for controlling the output voltage from 0.925V to 2.0V. Table 1 specifies the VOSENSE voltages for the 32 combinations of digital inputs. The LSB (B0) represents 50mV increments in the upper voltage range (2.00V to 1.30V) and 25mV increments in the lower voltage range (1.275V to 0.925V). Logic Low = GND, Logic High = VIDVCC or Float. VIDVCC (Pin 16): VID Input Supply Voltage. Range from 2.7V to 5.5V. Typically this pin is tied to INTVCC. EXTVCC (Pin 17): Input to the Internal Switch Connected to INTVCC. This switch closes and supplies VCC power whenever EXTVCC is higher than 4.7V. See EXTVCC connection in the Applications Information section. Do not exceed 7V on this pin. PGND (Pin 18): Driver Power Ground. This pin connects to the source of the bottom N-channel MOSFET, the anode of the Schottky diode and the (-) terminal of CIN. BG (Pin 19): High Current Gate Drive for Bottom N-Channel MOSFET. Voltage swing at this pin is from ground to INTVCC . INTVCC (Pin 20): Output of the Internal 5.2V Regulator and EXTVCC Switch. The driver and control circuits are powered from this voltage. This pin must be closely decoupled to power ground with a minimum of 4.7F tantalum or other low ESR capacitor. VIN (Pin 21): Main Supply Pin. This pin must be closely decoupled to power ground. SW (Pin 22): Switch Node Connection to Inductor and Bootstrap Capacitor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. BOOST (Pin 23): Supply to Topside Floating Driver. The bootstrap capacitor is returned to this pin. Voltage swing at this pin is from a diode drop below INTVCC to VIN + INTVCC. TG (Pin 24): High Current Gate Drive for Top N-Channel MOSFET. This is the output of a floating driver with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. 4 U U U LTC1736 FU CTIO AL DIAGRA COSC 6 PGOOD COSC 1 SYNC C 0.74V + 0.86V - 0V 2.4V gm =1.4m EA 0.86V SD RUN SOFT START + OVERCURRENT LATCH-OFF RC RUN/SS CSS 2 CC 3 ITH S Q R VOSENSE 10 VFB 9 100pF R1 SGND 5 0.8V R2 10k VFB - + VIDVCC INTVCC 16 2A 40k B4 15 B3 14 B2 13 B1 12 B0 11 VID DECODER 6V OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC1736 uses a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator I1 resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on Pin ITH, which is the output of the error amplifier EA. Pin VOSENSE, described in the Pin Functions, allows EA to receive an output feedback voltage VFB from the internal resistive divider. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until W VIN R4 21 VIN R3 0.25A - + 1.2V FORCE BOT DROP OUT DET TOP ON 0.55V + - 2k ICMP I1 - + SD 45k 45k - + I2 VIN 5.2V LDO REG IREV B 0.8V 4 FCB FC - + TOP F BOOST 23 TG 24 SW BOT SWITCH LOGIC 22 D1 CB 0.8V REF UVL INTVCC DB VSEC - + U U U + CIN OSC + CSEC * * VOUT - + - 6mV + BOT INTVCC 20 + COUT BURST DISABLE FC A + CINTVCC INTVCC 4(VFB) BUFFERED ITH 30k SLOPE COMP 30k 4.8V + - BG 19 PGND SENSE + 8 7 SENSE - EXTVCC 17 18 RSENSE 1736 FD the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from INTVCC through an external diode when the top MOSFET is turned off. As VIN decreases towards VOUT, the converter will attempt to turn on the top MOSFET continuously (`'dropout''). A dropout counter detects this condition and forces the top MOSFET to turn off for about 500ns every tenth cycle to recharge the bootstrap capacitor. 5 LTC1736 OPERATIO The main control loop is shut down by pulling Pin 2 (RUN/ SS) low. Releasing RUN/SS allows an internal 2A current source to charge soft-start capacitor CSS. When CSS reaches 1.3V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. If VOUT has not reached 70% of its final value when CSS has charged to 4.1V, latchoff can be invoked as described in the Applications Information section. The internal oscillator can be synchronized to an external clock applied to the FCB pin and can lock to a frequency between 90% and 130% of its nominal rate set by capacitor COSC. An overvoltage comparator OV guards against transient overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Foldback current limiting for an output shorted to ground is provided by amplifier A. As VFB drops below 0.6V, the buffered ITH input to the current comparator is gradually pulled down to a 0.86V clamp. This reduces peak inductor current to about 1/4 of its maximum value. Low Current Operation The LTC1736 has three low current modes controlled by the FCB control pin. Burst Mode operation is selected when the FCB pin is above 0.8V (typically tied to INTVCC). During Burst Mode operation, if the error amplifier drives the ITH voltage below 0.86V, the buffered ITH input to the current comparator will be clamped at 0.86V. The inductor current peak is then held at approximately 20mV/RSENSE (about 1/4 of maximum output current). If ITH then drops below 0.5V, the Burst Mode comparator B will turn off both MOSFETs to maximize efficiency. The load current will be supplied solely by the output capacitor until ITH rises above the 50mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by comparator F when the FCB pin is brought below 0.8V. 6 U (Refer to Functional Diagram) This forces continuous operation and can assist secondary winding regulation. When the FCB pin driven by an external oscillator, a cycleskipping operation is invoked and the internal oscillator is synchronized to the external clock by comparator C. In this mode the 25% minimum inductor current clamp is removed, providing constant frequency discontinuous operation over the widest possible output current range. This constant frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency operation. The FCB pin is tied to ground when forced continuous operation is desired. This operation is the least efficient mode, but is desirable in certain applications. The output can source or sink current in this mode. When forcing continuous operation and sinking current, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels-- BEWARE. Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff The RUN/SS capacitor, CSS, is used initially to limit the inrush current of each switching regulator. After the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, CSS is used as a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal output voltage, CSS begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing a > 5A pull-up at a compliance of 4V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of CSS during an overcurrent and/or shortcircuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. LTC1736 OPERATIO INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the internal circuitry of the LTC1736 is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5.2V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC is raised above 4.7V, the internal regulator is turned off and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source, such as the primary or a secondary output of the converter itself, to provide the INTVCC power. To provide clean start-up and to protect the MOSFETs, undervoltage lockout is used to keep both MOSFETs off until the input voltage is above 3.5V. APPLICATIO S I FOR ATIO The basic LTC1736 application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement, and begins with the selection of RSENSE. Once RSENSE is known, COSC and L can be chosen. Next, the power MOSFETs and D1 are selected. The operating frequency and the inductor are chosen based largely on the desired amount of ripple current. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple specification. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection For Output Current RSENSE is chosen based on the required output current. The LTC1736 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.5(INTVCC). The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. Allowing a margin for variations in the LTC1736 and external component values yields: U W U U U (Refer to Functional Diagram) VID Control Bits B0 to B4 are logic inputs setting the output voltage using an internal 5-bit DAC as a feedback resistive voltage divider. The output voltage can be set in 50mV or 25mV increments from 0.925V to 2.0V according to Table 1. Pins B0 to B4 are internally pulled up to VIDVCC. PGOOD A window comparator monitors the output voltage and its open-drain output is pulled low when the divided down output voltage is not within 7.5% of the reference voltage of 0.8V. RSENSE = 50mV IMAX COSC Selection for Operating Frequency and Synchronization The choice of operating frequency and inductor value is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The LTC1736 uses a constant-frequency architecture with the frequency determined by an external oscillator capacitor COSC. Each time the topside MOSFET turns on, the voltage on COSC is reset to ground. During the on-time, COSC is charged by a fixed current. When the voltage on the capacitor reaches 1.19V, COSC is reset to ground. The process then repeats. The value of COSC is calculated from the desired operating frequency assuming no external clock input on the FCB pin: 7 LTC1736 APPLICATIO S I FOR ATIO 1.61(107) - 11 COSC (pF ) = Frequency A graph for selecting COSC versus frequency is given in Figure 2. The maximum recommended switching frequency is 550kHz . The internal oscillator runs at its nominal frequency (fO) when the FCB pin is pulled high to INTVCC or connected to ground. Clocking the FCB pin above and below 0.8V will cause the internal oscillator to injection lock to an external clock signal applied to the FCB pin with a frequency between 0.9fO and 1.3fO. The clock high level must exceed 1.3V for at least 0.3s, and the clock low level must be less than 0.3V for at least 0.3s . The top MOSFET turn-on will synchronize with the rising edge of the clock. Attempting to synchronize to too high of an external frequency (above 1.3fO) can result in inadequate slope compensation and possible loop instability at high duty cycles. If this condition exists simply lower the value of COSC so (fEXT = fO) according to Figure 2. 100.0 87.5 75.0 COSC VALUE (pF) 62.5 50.0 37.5 25.0 12.5 0 0 100 200 300 400 500 OPERATING FREQUENCY (kHZ) 600 1736 F02 Figure 2. Timing Capacitor Value When synchronized to an external clock, Burst Mode operation is disabled but the inductor current is not allowed to reverse. The 25% minimum inductor current clamp present in Burst Mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. This constant 8 U frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency spectrum. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate-charge losses. In addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current IL decreases with higher inductance or frequency and increases with higher VIN or VOUT: W U U IL = V 1 VOUT 1 - OUT ( f)(L) VIN Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). Remember, the maximum IL occurs at the maximum input voltage. The inductor value also has an effect on low current operation. The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on. Lower inductor values (higher IL) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it Kool M is a registered trademark of Magnetics, Inc. LTC1736 APPLICATIO S I FOR ATIO is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool M. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1736: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.2V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1736 applications. The only exception is when low input voltage is expected (VIN < 5V); then, sublogic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1736 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: U Main Switch Duty Cycle = VOUT VIN VIN - VOUT VIN Synchronous Switch Duty Cycle = W U U The MOSFET power dissipations at maximum output current are given by: PMAIN = PSYNC ( ) (1+ )R + k(V ) (I )(C )( f) V -V = (I ) (1+ )R V VOUT IMAX VIN 2 IN 2 DS(ON) MAX RSS IN OUT 2 MAX IN DS(ON) where is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-Channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 3A to 5A regulators. The diode may be omitted if the efficiency can be tolerated. 9 LTC1736 APPLICATIO S I FOR ATIO CIN and COUT Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: V V IRMS IO(MAX ) OUT IN - 1 VIN VOUT 1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The selection of COUT is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. The output ripple (VOUT) is determined by: 1 VOUT IL ESR + 4fCOUT Where f = operating frequency, COUT = output capacitance, and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the I RIPPLE(P-P) requirement. With I L = 0.4IOUT(MAX) the output ripple will be less than 50mV at max VIN assuming: COUT required ESR < 2 RSENSE COUT > 1/(2fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly 10 U discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin loop compensation components can be modified to provide stable, high performance transient response regardless of the output capacitors selected. Manufacturers such as Nichicon, United Chemicon and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling, and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Panasonic SP and Sprague 595D series. Consult manufacturers for other specific recommendations. W U U LTC1736 APPLICATIO S I FOR ATIO INTVCC Regulator An internal P-channel low dropout regulator produces the 5.2V supply that powers the drivers and internal circuitry within the LTC1736. The INTVCC pin can supply a maximum RMS current of 50mA and must be bypassed to ground with a minimum of 4.7F tantalum, 10F special polymer or low ESR type electrolytic capacitor. Good bypassing is required to supply the high transient currents required by the MOSFET gate drivers. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1736 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional loading of INTVCC also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 5.2V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC current is supplied by the internal 5.2V linear regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC), and overall efficiency is lowered. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC1736GN is limited to less than 17mA from a 30V supply when not using the EXTVCC pin as follows: TJ = 70C + (17mA)(30V)(110C/W) = 126C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70C + (17mA)(5V)(110C/W) = 79C To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. EXTVCC Connection The LTC1736 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. U Whenever the EXTVCC pin is above 4.7V the internal 5.2V regulator shuts off, the switch closes and INTVCC power is supplied via EXTVCC until EXTVCC drops below 4.5V. This allows the MOSFET gate drive and control power to be derived from the output or other external source during normal operation. When the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 5V regulators this simply means connecting the EXTVCC pin directly to VOUT. However, for VID programmed regulators and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5.2V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected to an Output-Derived Boost Network. For this low output voltage regulator, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive boost winding or the capacitive charge pump circuits. Refer to the LTC1735 data sheet for details. The charge pump has the advantage of simple magnetics. 3. EXTVCC Connected to an External Supply (this option is the most likely used). If an external supply is available in the 5V to 7V range (EXTVCC VIN), it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. This is the typical case as the 5V power is almost always present and is derived by another high efficiency regulator. W U U 11 LTC1736 APPLICATIO S I FOR ATIO Output Voltage Programming The output voltage is digitally set to levels between 0.925V and 2.00V using the voltage identification (VID) inputs B0 to B4. The internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in 50mV or 25mV increments according to Table 1. The VID codes (00000-11110) are engineered to be compatible with Intel Mobile Pentium II processor specifications for output voltages from 0.925V to 2.00V. The LSB (B0) represents 50mV increments in the upper voltage range (2.00V to 1.30V) and 25mV increments in the lower voltage range (1.275V to 0.925V). The MSB is B4. When all bits are low, or grounded, the output voltage is 2.00V. Between the VFB pin and ground is a variable resistor, R1, whose value is controlled by the five input pins (B0 to B4). Another resistor, R2, between the VOSENSE and the VFB pins completes the resistive divider. The output voltage is thus set by the ratio of (R1 + R2) to R1. The LTC1736 has remote sense capability. The top of the internal resistive divider is connected to VOSENSE, and it is referenced to the SGND pin. This allows a kelvin connection for remotely sensing the output voltage directly across the load, eliminating any PC board trace resistance errors. Each VID digital input is pulled up by a 40k resistor in series with a diode from VIDVCC. Therefore, it must be grounded to get a digital low input, and can be either floated or connected to VIDVCC to get a digital high input. The series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than VIDVCC. The digital inputs accept CMOS voltage levels. VIDVCC is the supply voltage for the VID section. It is normally connected to INTVCC but can be driven from other sources. If it is driven from another source, that source MUST be in the range of 2.7V to 5.5V and MUST be alive prior to enabling the LTC1736. 12 U Table 1. VID Output Voltage Programming B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 2.000V 1.950V 1.900V 1.850V 1.800V 1.750V 1.700V 1.650V 1.600V 1.550V 1.500V 1.450V 1.400V 1.350V 1.300V * 1.275V 1.250V 1.225V 1.200V 1.175V 1.150V 1.125V 1.100V 1.075V 1.050V 1.025V 1.000V 0.975V 0.950V 0.925V ** Note: *, ** represents codes without a defined output voltage as specified in Intel specifications. The LTC1736 interprets these codes as a valid input and produces output voltage as follows: [01111] = 1.250V, [11111] = 0.900V. W U U LTC1736 APPLICATIO S I FOR ATIO Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. Note that the voltage across CB is about a diode drop below INTVCC. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage SW rises to VIN and the BOOST pin rises to VIN + INTVCC. The value of the boost capacitor CB needs to be 100 times greater than the total input capacitance of the topside MOSFET. In most applications 0.1F to 0.33F is adequate. The reverse breakdown on DB must be greater than VIN(MAX) . When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. SENSE +/SENSE - Pins The common mode input range of the current comparator is from 0V to 1.5(INTVCC). Continuous linear operation is guaranteed throughout this range allowing output voltages anywhere from 0.8V to 7V (although the VID control pins only program a 0.925V to 2.00V output range). A differential NPN input stage is used and is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This causes current to flow out of both sense pins to the main output. This forces a minimum load current which is sunk by the internal resistive divider resistors R1 and R2. The maximum current flowing out of the sense pins is: ISENSE + + ISENSE - = (2.4V - VOUT)/24k Remember to take this current into account if resistance is placed in series with the sense pins for filtering. Soft-Start/Run Function The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC1736. Soft-start reduces surge currents from VIN by gradually U increasing the controller's current limit ITH(MAX). This pin can also be used for power supply sequencing. Pulling the RUN/SS pin below 1.3V puts the LTC1736 into a low quiescent current shutdown (IQ < 20A). This pin can be driven directly from logic as shown in Figure 3. Releasing the RUN/SS pin allows an internal 2A current source to charge up the external RUN/SS capacitor CSS. If RUN/ SS has been pulled all the way to ground there is a delay before starting of approximately: W U U t DELAY = 1.3V CSS = 650ms / F CSS 2A ( ) When the voltage on RUN/SS reaches 1.3V the LTC1736 begins operating with a current limit at approximately 25mV/RSENSE. As the voltage on RUN/SS increases from 1.3V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 850ms/F to reach full current. The output current thus ramps up slowly reducing the starting surge current required from the input power supply. Diode D1 in Figure 3 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. This diode and CSS can be deleted if soft-start is not needed. The RUN/SS pin has an internal 6V zener clamp (See Functional Diagram). 3.3V OR 5V D1 CSS (a) (b) CSS 1736 F03 RUN/SS RUN/SS Figure 3. RUN/SS Pin Interfacing Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to shut off the controller and latchoff when an overcurrent condition is detected. The RUN/SS capacitor CSS is used initially to turn on and limit the inrush current of the controller. After the controller has been started and given adequate time to charge up the output capacitor and provide full load 13 LTC1736 APPLICATIO S I FOR ATIO current, CSS is used as a short-circuit timer. If the output voltage falls to less than 70% of its nominal output voltage after CSS reaches 4.1V, the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and CSS begins discharging. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing > 5A at a compliance of 4V to the RUN/SS pin as shown in Figure 4. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5A current from VIN as in Figure 4a, current latchoff is always defeated. Diode connecting this pull-up resistor to INTVCC , as in Figure 4b, eliminates any extra supply current during controller shutdown while eliminating the INTVCC loading from preventing controller startup. If the voltage on CSS does not exceed 4.1V, the overcurrent latch is not armed and the function is disabled. INTVCC RSS RUN/SS D1 RSS CSS 1736 F04 VIN 3.3V OR 5V D1 RUN/SS CSS (a) (b) Figure 4. RUN/SS Pin Interfacing with Latchoff Defeated Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. Defeating this feature will easily allow troubleshooting of the circuit and PC layout. The internal shortcircuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. After the design is complete, a decision can be made whether to enable the latchoff feature. The value of the soft-start capacitor CSS will need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: 14 U CSS > (COUT )(VOUT)(10 - 4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1F will be sufficient for most applications. Fault Conditions: Current Limit and Current Foldback The LTC1736 current comparator has a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. The LTC1736 includes current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is defeated. If the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mV to 30mV. Under short-circuit conditions with very low duty cycle, the LTC1736 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be conducting the peak current. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC1736 (approximately 200ns), the input voltage, and inductor value: IL(SC) = tON(MIN) VIN /L. The resulting short circuit current is: ISC = 30mV 1 + IL(SC) RSENSE 2 The current foldback function is always active and is not effected by the current latchoff function. Fault Conditions: Output Overvoltage Protection (Crowbar) The output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. This condition causes huge currents to flow, much greater than in normal operation. This feature is designed to protect against a shorted top MOSFET; it does not protect against a failure of the controller itself. The comparator (OV in the Functional Diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed the top W U U LTC1736 APPLICATIO S I FOR ATIO MOSFET is turned off and the bottom MOSFET is forced on. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automatically resumes. Note that VID controlled output voltage decreases may cause the overvoltage protection to be momentarily activated. This will not cause permanent latchoff nor will it disrupt the desired voltage change. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest amount of time that the LTC1736 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit and care should be taken to ensure that: tON(MIN) < VOUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1736 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and voltage will increase. The minimum on-time for the LTC1736 in a properly configured application is generally about 200ns. However, as the peak sense voltage decreases, the minimum ontime gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum ontime limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule keep the inductor ripple current equal or greater than 40% of IOUT(MAX) at VIN(MAX). FCB Pin Operation When DC voltage on the FCB pin drops below its 0.8V threshold, continuous mode operation is forced. In this U case, the top and bottom MOSFETs continue to be driven synchronously regardless of the load on the main output. Burst Mode operation is disabled and current reversal is allowed in the inductor. In addition to providing a logic input to force continuous synchronous operation and external synchronization, the FCB pin provides a means to regulate a flyback winding output. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom synchronous switch is on. When primary load currents are low and/or the VIN/VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings provided there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary output may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in the Functional Diagram by the turns ratio N of the transformer: VSEC (N + 1) VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN): W U U R4 VSEC(MIN) 0.8 V 1 + R3 If VSEC drops below this level, the FCB voltage forces continuous switching operation until VSEC is again above its minimum. In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.25A internal current source pulling the pin high. Remember to include this current when choosing resistor values R3 and R4. 15 LTC1736 APPLICATIO S I FOR ATIO The internal LTC1736 oscillator can be synchronized to an external oscillator by applying an clocking the FCB pin with a signal above 1.5VP-P. When synchronized to an external frequency, Burst Mode operation is disabled, but cycle skipping is allowed at low load currents since current reversal is inhibited. The bottom gate will come on every 10 clock cycles to assure the boostrap cap is kept refreshed. The rising edge of an external clock applied to the FCB pin starts a new cycle. The range of synchronization is from 0.9fO to 1.3fO, with fO set by Cosc. Attempting to synchronize to a higher frequency than 1.3fO can result in inadequate slope comensation and cause loop instability with high duty cycles. If loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing COSC. The following table summarizes the possible states available on the FCB pin: Table 2 FCB Pin DC Voltage: 0V to 0.7V DC Voltage: > 0.9V Feedback Resistors Condition Burst Disabled/Forced Continuous Current Reversal Enabled Burst Mode Operation, No Current Reversal Regulating a Secondary Winding Ext Clock: (0V to VFCBSYNC) Burst Mode Operation Disabled (VFCBSYNC > 1.5V) No Current Reversal Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC1736 circuits: 1) LTC1736 VIN current, 2) INTVCC current, 3) I2R losses, 4) Topside MOSFET transition losses, 5) Other losses. 16 U 1. The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (< 1%) loss that increases with VIN. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom-side MOSFETs. By powering EXTVCC from an output-derived source (or other high efficiency source), the additional VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For example, in a 15V to 1.8V application, 10mA of INTVCC current results in approximately 1.2mA of VIN current. This reduces the midcurrent loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R Losses are predicted from the DC resistances of the MOSFET, inductor and current shunt. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the topside main MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.02, RL = 0.03, and RSENSE = 0.01, then the total resistance is 0.06. This results in losses ranging from 3% to 17% as the output current increases from 1A to 5A for a 1.8V output, or 4% to 20% for a 1.5V output. Efficiency varies as the inverse square of VOUT for the same external components and power level. I2R losses cause the efficiency to drop at high output currents. 4. Transition losses apply only to the topside MOSFET(s), and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: W U U LTC1736 APPLICATIO S I FOR ATIO Transition Loss = (1.7)(VIN2)(IO(MAX))(CRSS)(f) 5. Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20F to 40F of capacitance having a maximum of 0.01 to 0.02 of ESR. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been U determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full-load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/DC ratio cannot be used determine phase margin. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (> 1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA. Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load dump, reverse battery, and double battery. Load dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes W U U 17 LTC1736 APPLICATIO S I FOR ATIO several hundred milliseconds to decay. Reverse battery is just what it says, while double battery is a consequence of tow truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 5 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive battery line. The series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC1736 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V VIN LTC1736 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 1736 F05 Figure 5. Plugging into the Cigarette Lighter Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V(nominal), 2.0V to 1.5V range, IMAX = 12A and f = 300kHz. RSENSE and COSC can immediately be calculated: RSENSE = 50mV/12A = 0.0042 COSC = 1.61(107)/(300kHz) - 11pF = 43pF Assume a 2H inductor and check the actual value of the ripple current. The following equation is used : V V IL = OUT 1 - OUT VIN ( f)(L) The highest value of the ripple current occurs at the maximum input and output voltages: 18 U IL = 2V 2V 1- = 5A 300kHz(1.2H) 22V W U U The maximum ripple current is 42% of maximum output current, which is about right. Next, verify the minimum on-time of 200ns is not violated. The minimum on-time occurs at maximum VIN and minimum VOUT. tON(MIN) = VOUT VIN(MAX ) f () = 1.5V = 227ns 22V(300kHz) The power dissipation on the topside MOSFET can be easily estimated. Choosing a Fairchild FDS6612A results in: RDS(ON) = 0.03, CRSS = 80pF. At maximum input voltage with T(estimated) = 50C: PMAIN = = 635mW ( ) [1+ (0.005)(50C - 25C)](0.03) +1.7(22V ) (12A )(80pF )(300kHz) 1.8V 12 22V 2 2 Because the duty cycle of the bottom MOSFET is much greater than the top, two larger MOSFETs must be paralleled. Choosing Fairchild FDS6680A MOSFETs yields a parallel RDS(ON) of 0.0065. The total power dissipaton for both bottom MOSFETs, again assuming T = 50C, is: PSYNC = 22V - 1.8V 12A 22V = 945mW ( ) (1.1)(0.0065) 2 Thanks to current foldback, the bottom MOSFET dissipaton in short circuit will be less than under full-load conditions. CIN is chosen for an RMS current rating of at least 2.5A at temperature. COUT is chosen with an ESR of 0.01 for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR(IL) = 0.01(5A) = 50mVP-P LTC1736 APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1736. These items are also illustrated graphically in the layout diagram of Figure 6. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1736 signal ground pin must return to the (-) plate of COUT. The power ground connects to the source of the bottom N-channel MOSFET, anode of the Schottky diode and (-) plate of CIN, which should have as short lead lengths as possible. 2. Does the VOSENSE pin connect directly to the (+) plate of COUT? The 100pF capacitor from VFB to SGND should be as close as possible to the LTC1736. 3. Are the SENSE - and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE - should be as close as possible to the LTC1736. + COSC 1 CSS RC CC2 CC 2 3 4 5 100pF 1000pF 6 7 8 9 10 11 12 COSC RUN/SS ITH FCB SGND PGOOD SENSE - SENSE + VFB VOSENSE B0 B1 LTC1736 TG BOOST SW VIN 24 23 22 21 20 19 18 17 16 15 14 13 L1 D1 DB CB M2 4.7F M1 CIN VIN INTVCC BG PGND EXTVCC VIDVCC B4 B3 B2 + EXTERNAL EXTVCC CONNECTION + Figure 6. LTC1736 Layout Diagram + U 4. Does the (+) plate of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). 5. Is the INTVCC decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. 6. Keep the switching node (SW), Top Gate node (TG) and Boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the "output side" (Pins 13 to 24) of the LTC1736 and occupy minimum PC trace area. - - COUT RSENSE VOUT W U U + 1736 F06 19 LTC1736 TYPICAL APPLICATIO 12A Converter with External Clock Synchronization for CPU Power Optimized for VOUTs of 1.3V to 1.5V COSC 56pF 1 CSS 01.F RC 33k CC2 220pF CC 470pF 2 3 4 5 6 7 100pF 1000pF 8 9 10 11 12 COSC RUN/SS ITH FCB SGND PGOOD SENSE - SENSE + VFB VOSENSE B0 B1 LTC1736 TG BOOST SW VIN 24 23 22 21 20 19 18 17 16 15 14 13 OUTPUT VOLTAGE PROGRAMMING OPTIONAL: CONNECT TO 5V CB 0.22F DB CMDSH-3 M1 FDS6680A L1 1.5H VIN 4.75V TO 24V EXT CLOCK 250kHz RELATED PARTS PART NUMBER LTC1147 LTC1148HV/LTC1148 LTC1149 LTC1159 LTC1174 LTC1265 LTC1266 LT1375/LT1376 LTC1433/LTC1434 LTC1435/LTC1435A LTC1436/LTC1436-PLL LTC1474/LTC1475 LTC1735 DESCRIPTION High Efficiency Step-Down Controller High Efficiency Synchronous Step-Down Controllers High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller Monolithic 0.6A Step-Down Switching Regulator 1.2A Monolithic High Efficiency Step-Down Switching Regulator High Efficiency Synchronous Step-Down Controller, N-Ch Drive 1.5A 500kHz Step-Down Switching Regulators Monolithic 0.45A Low Noise Current Mode Step-Down Switching Regulator High Efficiency Synchronous Step-Down Controllers, N-Ch Drive High Efficiency Low Noise Synchronous Step-Down Converters, N-Ch Drive Ultralow Quiescent Current Step-Down Monolithic Switching Regulators High Efficiency Synchronous Step-Down Controller, N-Ch Drive COMMENTS 100% DC, Burst Mode Operation, 8-Pin 100% DC, Burst Mode Operation, VIN < 20V 100% DC, Std Threshold MOSFETs, VIN < 48V 100% DC, Logic Level MOSFETs, VIN < 40V 100% DC, Burst Mode Operation, 8-Pin SO 100% DC, Burst Mode Operation, 14-Pin SO 100% DC, Burst Mode Operation, VIN < 20V High Efficiency 16-Pin Narrow, 20-Pin Narrow SSOP Burst Mode Operation, 16-Pin Narrow SO Adaptive PowerTM Mode 20-Pin, 24-Pin SSOP 100% DC, 8-Pin MSOP Burst Mode Operation, 16-Pin Narrow SSOP Adaptive Power is a trademark of Linear Technology Corporaton. 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U + CIN 22F/30V x3 OS-CON RSENSE 0.004 INTVCC BG PGND EXTVCC VIDVCC B4 B3 B2 + 4.7F M2 FDS6680A x2 D1 MBRD835L + COUT 180F/4V x3 VOUT 1.3V TO 1.5V 12A SGND 10 10 1736 TA02 1736p LT/LT 1298 * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1998 |
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